The present invention relates generally to data processing systems and, more particularly, to an apparatus and method for capturing source synchronous data.
With the advent of high-speed, parallel data interfaces, traditional edge clocking techniques of providing xe2x80x9csetup and holdxe2x80x9d around a capturing clock edge have proven to be increasingly more difficult to implement. As a result, source synchronous designs have been utilized to reduce the variations in timing interface between communicating components in a computer system.
In source synchronous clocking, the data and clock signals are initially synchronized at the transmitting logic components, thus eliminating from the transmitting logic components the burden of accurately centering a clock edge within a xe2x80x9cdata valid regionxe2x80x9d. However, various processing and environmental conditions can cause the clock edge to be skewed relative to the data at the receiving logic, thereby resulting in an uncertainty of the relationship between data and clock. The positioning of the clock within the data valid region has thus become the responsibility of the receiving components. Such accurate positioning can be difficult to achieve due to the wide range of process variations and the effect they have on circuit delays.
During the transmission of data, a data cycle is defined wherein the first segment of the data cycle represents a xe2x80x9cdata uncertainty regionxe2x80x9d, with the remaining segment of the data cycle representing a xe2x80x9cdata valid regionxe2x80x9d. Ideally, the edge (rising or falling) of the clock signal should arrive at some point during the data valid window segment of the data cycle to ensure the correct capture of data by the receiving component. Accordingly, the clock signal may be intentionally delayed until after the data uncertainty region has passed. Unfortunately, the delay elements traditionally used to correctly position the clock signal edge also have process variations introduced therein. These process variations can cause the delay elements to vary by as much as xc2x150%, and result in the clock edge arriving too early (i.e., during the data uncertainty region of the present data cycle) or too late (i.e., during the data uncertainty window of the next data cycle). In such a situation, the whole purpose of implementing a clock signal delay element would be defeated.
The above discussed and other drawbacks and deficiencies of the prior art are overcome or alleviated by an apparatus for capturing a data signal sent from a transmitting source to a receiving element, the data signal being accompanied by a first clock signal in a source synchronous system. In an exemplary embodiment, the apparatus comprises a delay element having an input coupled to the first clock signal and an output producing a delayed first clock signal. The delay element further includes a plurality of delay latches, having a second clock signal as a clock input thereto, the second clock signal having a frequency which is a multiple of the frequency of the first clock signal. The data signal is captured by the receiving element when the receiving element is triggered by an edge of the delayed first clock signal.
In preferred embodiment of the invention, the apparatus includes a first stage of four parallel connected delay latches, each of the first stage of four parallel connected delay latches having an input coupled to the first clock signal. A second stage of four parallel connected delay latches is also included, with each of the second stage of four parallel connected delay latches having an input coupled to a corresponding output of the first stage of four parallel connected delay latches. Each of the four parallel connected delay latches within the first and second stages has a second clock frequency of 2.5 times the frequency of the first clock signal, with the second clock signal being applied to each delay latch 90 degrees out of phase with respect to one another in the first and second stages.